1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
Recent progress in high integration of semiconductor devices has generalized the utilization of multi-layered interconnect in the semiconductor devices. In addition, interconnects and connection holes (contact holes and via holes) are increasingly downsized along with miniaturization of the semiconductor devices, making it more difficult to sufficiently fill interconnecting material into the connection holes. Insufficient filling of connection holes causes bad effects such as a break in interconnection and occurrence of a contact pit. Hence, a conductive barrier metal layer is formed before deposition of an interconnecting material such as Al—Si or Al—Si—Cu. The barrier metal layer is generally formed by depositing Ti or both Ti and TiN by chemical vapor deposition (CVD) Because Ti has better heat resistance and auto-flatness than Al and the like described above, Ti is effective in eliminating the negative effects described above.
The procedure for manufacturing interconnection and connection holes in a conventional semiconductor device is described with reference to FIGS. 2A to 2D.
A first interlayer insulating film 102 and a second interlayer insulating film 101 are formed on a semiconductor substrate 103 by chemical vapor deposition (CVD). A TEOS, a silicon oxide film (BPSG film) including boron and phosphorus, or the like is used for these interlayer insulating films (FIG. 2A).
Next, a contact hole is formed in these interlayer insulating films. Herein, a method of improving coverage of an interconnecting material is described from among several methods of forming a contact hole. First, a resist film 107 is used as a mask and isotropic etching is performed up to a certain depth to expand an opening of a contact hole, and then anisotropic etching is performed to form the contact hole (FIG. 2B).
Subsequently, a barrier metal layer 104 is formed in the connection hole, and an interconnecting material 106 is deposited thereon. Further, a mask pattern is formed on the interconnecting material 106 by a photolithography process to form an interconnect pattern by etching (FIGS. 2C and 2D). (See, for example, JP08-330252 A.)